For test of digital devices, in most cases digital random logic is tested via scan test or Logic Built-in Self Test (LBiST). Both test categories rely on scan chains that allow to shift in test patterns and shift out test results. If shifting through scan chains is blocked by a defect, scan test and LBiST is disturbed and as an outcome of that test, coverage is often considerably reduced. A fast blocked chain analysis is needed that identifies two successive scan cells with the blocking defect in between. Then further fault analysis can be used to find the root cause for the defect and to solve the problem and improve yield.
Additional hardware on the device under test (DUT) that is added during the design process is considered as too costly since such techniques typically require a considerable amount of die area.
It is inherent in the problem of blocked scan chains that without additional hardware the fault location cannot be identified correctly and unambiguously in some cases.
There exist software solutions that perform a blocked chain analysis, but usually require a valid simulation model of the DUT that has to be configured correctly for analysis. Furthermore, a considerable computing power is required to simulate the behavior of a modern design, so it might take minutes, hours or even days. In order to handle ambiguous results, some software solutions provide a confidence level for their results.
For blocked chain analysis Inovys has filed a patent (U.S. Pat. No. 7,568,139) that describes how to implement on a test apparatus a well known process to analyze scan chains that are blocked by permanent defects. However, this solution is not able to handle ambiguous results, in such a case it can report an incorrect faulty site.